Huawei unveils Tau Scaling Law + LogicFolding chip architecture
Huawei unveiled a chip design called Tau Scaling Law plus LogicFolding architecture at IEEE ISCAS 2026 in Shanghai. Goal: match 1.4nm transistor performance without advanced lithography, targeting 2031. China's commercial best is currently around 7nm. Source: SCMP
Huawei has unveiled a chip design approach called the Tau Scaling Law alongside a new chip architecture named LogicFolding, presented at the IEEE International Symposium on Circuits and Systems (ISCAS) 2026 in Shanghai. The premise is a departure from the standard playbook of shrinking transistors. Instead, Huawei is focused on shortening the time constant inside chips to reduce signal delays and improve performance and efficiency. The company says the approach should deliver transistor performance equivalent to a 1.4-nanometre process node without depending on the advanced lithography tools that U.S. export controls keep out of China. The stated timeline is the early 2030s, with self-developed high-end chips equivalent to 1.4nm processes projected by 2031. China's most advanced commercially proven chipmaking capability today sits around the 7-nanometer level, mainly delivered by SMIC using older deep ultraviolet lithography systems. The path still faces hurdles. Huawei needs new chip-design tools suited to the Tau Scaling approach, and overheating remains a major challenge. Sources: - South China Morning Post: https://www.scmp.com/tech/article/3354710/huawei-unveils-new-scaling-law-and-tech-can-develop-14-nm-equivalent-chips-2031 - NBC News: https://www.nbcnews.com/world/asia/chinas-huawei-touts-chip-design-breakthrough-bid-defy-us-sanctions-rcna346783