Huawei unveils Tau Scaling Law and LogicFolding at IEEE ISCAS Shanghai, targets 1.4nm-class chips by 2031
Huawei announced a roadmap Monday at IEEE ISCAS in Shanghai to design 1.4nm-class chips by 2031, three years behind TSMC $TSM. HiSilicon head He Tingbo unveiled a Tau Scaling Law and LogicFolding architecture, jumping transistor density from 155 to 238 MTr per square millimeter.
Huawei used a keynote at IEEE ISCAS in Shanghai on May 25 to lay out the most detailed semiconductor roadmap it has published under U.S. export controls. HiSilicon president He Tingbo said the firm now aims to design chips with transistor density equivalent to a 1.4-nanometer node by 2031. TSMC $TSM has said it plans to mass produce the same generation by 2028. The keynote introduced two concepts. The Tau Scaling Law replaces traditional geometric scaling with a time-based scaling principle for both chips and electronic systems. The LogicFolding architecture is described as a layout technique that lifts transistor density from 155 to 238 million transistors per square millimeter in a single step. Huawei says it has already designed and produced 381 chips on the Tau principle over the past six years. The first Kirin chips using LogicFolding are scheduled to launch in Fall 2026. The announcement lands as Nvidia $NVDA CEO Jensen Huang told CNBC his company has largely conceded China's AI chip market to Huawei, citing record local-ecosystem growth. Sources: Huawei newsroom, Tom's Hardware, SemiWiki.